A typical electronic switch in an integrated circuit with complementary MOS transistors (CMOS) is provided by an n-channel transistor and by a p-channel transistor each having its source and drain terminals connected, respectively, to the drain and source terminals of the other. The switch is controlled by control signals which are applied to the gate terminals of the two transistors in phase opposition to make the two transistors conductive or cut them off simultaneously.
FIG. 1 shows, in section, a portion of an integrated circuit in which an electronic switch with CMOS transistors is formed. FIG. 2 is an electrical diagram of a circuit which comprises the electronic switch of FIG. 1. In a p-type monocrystalline silicon substrate, indicated 10, there is an n-type region or n-well 11 which has, at its bottom, a buried region 12 which is strongly doped, and, hence, indicated N+. A deep contact region 13, which is also a strongly doped n-type region, extends from the surface of the substrate as far as the buried region 12. In the n-well 11, there is a p-type region or p-well 14 in which there are two strongly doped n-type regions 15, 16, which provide the source and drain regions of an n-channel transistor, and a strongly doped p-type region 17.
On top of the channel which separates the source and drain regions 15 and 16, there is a strip of electrically-conductive material (doped polysilicon or metal) 18, separated from the surface of the substrate by a layer of dielectric material, for example, silicon dioxide. The strip 18 provides the gate electrode of the n-channel transistor which is indicated M1 in the drawings.
In the n-well 11 there are also two strongly doped P+ regions, indicated 20 and 21, which provide the source and drain regions of a p-channel transistor. On top of the channel which separates the regions 20 and 21, there is a gate electrode 22, separated from the substrate by a dielectric layer as that of the n-channel transistor described above. The p-channel transistor is indicated M2 in the drawings.
Metal electrodes for the connection and biasing of the various regions are formed on the front surface of the substrate on the regions 13, 17, 16, 15, 21 and 20. An electrode is also provided on the bottom surface for biasing the substrate 30. In particular, the drain region 16 of the n-channel transistor M1 and the source region 20 of the p-channel transistor M2 are connected together to an input terminal, indicated IN, of the electronic switch. The source region 15 of the transistor M1 and the drain region 21 of the transistor M2 are connected together to an output terminal, indicated OUT, of the electronic switch. The gate electrodes 18 and 22 of the two transistors M1 and M2 provide two control terminals, indicated G1 and G2 of the electronic switch. The regions 13 and 17 are connected to respective supply terminals, indicated +Vcc and GND. The bottom surface of the substrate 10 is also connected to the supply terminal GND.
FIG. 2 shows a power MOS transistor MP with its source-drain path in series with a load Z between the terminals of a voltage supply, indicated GND and +Vcc. An electronic switch such as that of FIG. 1 is connected between the point at which the load Z is connected to the drain of the power transistor MP and a circuit S, generally indicated by its impedance towards ground, that is, towards the terminal GND. The circuit S, for example, may be a sampling circuit. The control terminals G1 and G2 are connected, respectively, to the input and to the output of an inverter INV so that a control signal .PHI. applied to the terminal G1 is present, inverted, as negated .PHI. at the terminal G2. In this example, a positive voltage greater than the conduction threshold of the transistor M1, that is, a "high" logic signal, applied to the terminal G1, makes the n-channel transistor M1 conductive and is present as a "low" logic signal at the control terminal G2, also making the p-channel transistor M2 conductive. In these conditions, the electronic switch is closed, in the opposite conditions, it is open.
The electronic switch operates correctly, that is, it is opened by a low-level signal at the control terminal G1 and closed by a high-level signal at the same terminal, if the input voltage remains between the ground level and the level of the positive supply voltage +Vcc. It should be noted that, for correct operation of the integrated circuit, the regions 17 and 13, as well as the substrate 10, have to be biased by the connection of the terminals indicated GND and +Vcc to a power supply.
If, however, the input voltage goes beyond these levels, that is, if it becomes negative or exceeds the supply voltage +Vcc when the switch is in the open state, as occurs if the load Z is inductive, the switch is not perfectly insulated. The cause of this is to be found in the integrated structure of the electronic switch.
In fact, the regions 16, 14 and 11 together form two p-n junctions which together define a lateral npn-type bipolar transistor, indicated T1, represented by broken lines in FIG. 2. Similarly, the regions 16, 14 and 15 together define another lateral npn bipolar transistor T2, and the regions 21, 11 and 20 together define a lateral pnp bipolar transistor T3, also represented by broken lines in FIG. 2. The regions 20, 11 and the substrate 10 together define a lateral pnp bipolar transistor T4.
As can easily be confirmed, the parasitic transistors T1, T2, T3 and T4 are cut off when the input signal does not go beyond the aforementioned limits. However, the parasitic transistors become conductive if these limits are passed.
In particular, if the voltage at the terminal IN goes below the ground level, that is, if it becomes negative by an amount greater than the threshold voltage (Vbe) of the transistor T1 or of the transistor T2, that transistor becomes conductive. The conduction of T1 does not interfere with the insulation of the electronic switch because its collector current originates from the supply, but the conduction of the transistor T2 causes an injection of current from the output terminal OUT to the input terminal IN, that is, a leakage current of the switch, because the collector of T2 is connected to the output terminal OUT.
Similarly, if the voltage at the input IN exceeds the supply voltage +Vcc by an amount greater than the threshold voltage of the pnp transistors T3 and T4, these become conductive. The conduction of T4, like that of T1, does not interfere with the insulation of the electronic switch, but the conduction of T3 produces a leakage current of the switch from the input terminal IN to the output terminal OUT.
To prevent or at least attenuate the insulation leakages described above, it would be necessary to increase the distance between the regions which together form the parasitic transistors T1, T2, T3 and T4. This can be done only with regard to the transistors T1 and T4 which, however, cause only leakages towards the supply. Unfortunately, this cannot be done for the transistors T2 and T3, because this would require a modification of the characteristics of the MOS transistors M1 and M2.